verilog dflipflop代码的意外结果

对于下面的verilog dff,最后显示示例输出(仅显示前两行)。我无法理解为什么always块在时间0时执行,而我已经编写了always@(posedge clk)。posedge clk在时间零点不发生。你能帮我理解输出吗?

module main;
reg d,clk;
wire q;

always #5 clk++;
always #10 d++;

dff dff(d,clk,q);  

initial 
begin
d = 1;
clk = 1;
$monitor("time = %d d = %d clk = %d q = %d",$time,d,clk,q);
#50 $finish ;
end
endmodule

module dff(input wire d,clk, output reg q);
always @(posedge clk)
begin
q = d;
$display("time = %d inside module dff",$time);
end
endmodule

Output is
time =                    0 inside module dff
time =                    0 d = 1 clk = 1 q = 1
...