VHDL 8x16寄存器文件不可合成

但我得到了这些错误:

Error line 26 : syntax error
vbl_bcomp_y.y 4464 : Error 18 line 26 in file regfile :illegal concurrent statement
Note that errors might also be due to unsupported statements

vasy

-- ...

architecture RTL of REGFILE is
  type t_regfile is array (0 to 7) of std_logic_vector(15 downto 0);
  signal reg : t_regfile := (others => X"0000"); -- Init with 0
begin
  process (clk)
  begin
    if rising_edge(clk) then
      if load_lo = '1' then
        -- The error line 
        reg (to_integer(unsigned(in_sel))) (7 downto 0) <= in_data (7 downto 0);
      end if;
      if (load_hi = '1') then
        reg (to_integer (unsigned (in_sel))) (15 downto 8) <= in_data (15 downto 8);
      end if;
    end if;
  end process;

  process (out0_sel, out1_sel, reg)
  begin
    out0_data <= reg (to_integer(unsigned(out0_sel)));
    out1_data <= reg (to_integer (unsigned(out1_sel)));
  end process;
end RTL;