您的代码可以在VHDL中“原样”使用。
sra公司
在-2008之前的IEEE包numeric_std中未定义。您的代码将使用与-2008兼容的VHDL实现进行分析,不会出错
否则,对于以前版本兼容的实现:
outp <= unsigned (to_stdlogicvector(to_bitvector(std_logic_vector(inp)) sra to_integer(samt)));
因为
sra
为bit_vector类型预定义
samt
是无符号类型(具有具有自然范围的等效二进制值)。
您还缺少一个符合合成条件的RTL对顺序逻辑的描述-未标记的过程具有
clk
在它的敏感度列表中。
在2008年以前兼容的VHDL实现中更改并显示上述修复:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity barrelshifter is
port (
clk: in std_logic;
inp: in unsigned (31 downto 0):= (others => '0');
s: in unsigned (6 downto 0);
outp: out unsigned (31 downto 0)
);
end entity barrelshifter;
architecture behavioral of barrelshifter is
signal samt: unsigned (4 downto 0);
signal stype: unsigned (1 downto 0);
signal inp1: unsigned (31 downto 0);
begin
samt <= s(6 downto 2);
stype <= s(1 downto 0);
inp1 <= inp;
UNLABELLED:
process(clk)
begin
if rising_edge(clk) then
if stype = "00" then
outp <= inp sll to_integer(samt);
end if;
if stype = "01" then
outp <= inp srl to_integer(samt);
end if;
if stype = "10" then
outp <= unsigned (to_stdlogicvector(to_bitvector(std_logic_vector(inp)) sra to_integer(samt)));
end if;
if stype = "11" then
outp <= inp ror to_integer(samt);
end if;
end if;
end process;
end architecture behavioral;
因为if语句的条件取决于
stype
可以用case语句替换内部if语句,或者用elsif替换条件替换单个if语句。这将允许在第一个匹配值
手写笔
.
看起来是这样的:
architecture with_elsif of barrelshifter is
signal samt: unsigned (4 downto 0);
signal stype: unsigned (1 downto 0);
signal inp1: unsigned (31 downto 0);
begin
samt <= s(6 downto 2);
stype <= s(1 downto 0);
inp1 <= inp;
UNLABELLED:
process(clk)
begin
if rising_edge(clk) then
if stype = "00" then
outp <= inp sll to_integer(samt);
-- end if;
elsif stype = "01" then
outp <= inp srl to_integer(samt);
-- end if;
elsif stype = "10" then
outp <= unsigned (to_stdlogicvector(to_bitvector(std_logic_vector(inp)) sra to_integer(samt)));
-- end if;
elsif stype = "11" then
outp <= inp ror to_integer(samt);
end if;
end if;
end process;
end architecture with_elsif;
或者这个:
architecture with_case of barrelshifter is
signal samt: unsigned (4 downto 0);
signal stype: unsigned (1 downto 0);
signal inp1: unsigned (31 downto 0);
begin
samt <= s(6 downto 2);
stype <= s(1 downto 0);
inp1 <= inp;
UNLABELLED:
process(clk)
begin
if rising_edge(clk) then
case stype is
when "00" =>
outp <= inp sll to_integer(samt);
when "01" =>
outp <= inp srl to_integer(samt);
when "10" =>
outp <= unsigned (to_stdlogicvector(to_bitvector(std_logic_vector(inp)) sra to_integer(samt)));
when "11" =>
outp <= inp ror to_integer(samt);
when others =>
end case;
end if;
end process;
end architecture with_case;
所有这些代码示例都会进行分析。这三种架构尚未被模拟,我们鼓励您这样做,以确保运营商做到您所期望的。
通常,您应该使用包numeric_std中定义的shift_right、shift_left、rotate right和rotate left函数。
