在VHDL返回错误中添加两位_向量”(vcom-1581)中缀运算符“+”没有可行项

如果使用ieee,可以添加位向量。数字位无符号。所有这些都是VHDL-2008的一部分。您正在使用的numeric\u std包没有定义位向量的加法。

如果发现旧CAD实验室软件不支持numeric\u bit\u unsigned,则可以使用类型转换,numeric\u bit包含有符号和无符号类型的声明:

library ieee;
use ieee.numeric_bit.all;

entity bin2bcd is
    port (bin : in bit_vector(3 downto 0) := "0000";
        clk : in bit;
        bcdout : out bit_vector(4 downto 0) := "00000");
end bin2bcd;

architecture bin2bcdarch of bin2bcd is
begin
    process(clk)
    variable gt9 : bit;
    variable temp : unsigned(3 downto 0) := "0110";  -- was bit_vector
    variable bcdout_temp : unsigned(4 downto 0);     -- was bit vector
    begin 
        if clk'event and clk = '1' then
            gt9 := bin(3) and(bin(2) or bin(1));
            if gt9 = '1' then
                bcdout_temp := '0' & unsigned(bin) + ('0' & temp);  -- type conversion
            else
                bcdout_temp := '0' & unsigned(bin); -- type conversion
            end if;
        end if;
    bcdout <= bit_vector(bcdout_temp);  -- type conversion
    end process;
end bin2bcdarch;

注:温度也可以是类常数而不是变量,除了初始值之外,它不被赋值。

从您使用WARP2进行合成(可能是复杂可编程逻辑器件)的评论中,我记得它最初是为了使用AHDL作为输入描述而开发的,对VHDL和Verilog的支持是后来才想到的。

您可能会看到基于VHDL结构映射到合成支持的AHDL结构的限制。

处理此类限制的方法可能是将设计中的麻烦部分描述为数据流描述:

entity bin2bcd is
    port (
        bin:    in  bit_vector(3 downto 0);
        clk:    in  bit;
        bcdout: out bit_vector(4 downto 0)
    );
end entity bin2bcd;

architecture dataflow of bin2bcd is
    signal bcdout_temp:     bit_vector(4 downto 0);
begin

    bcdout_temp(4) <=  bin(3) and ( bin(2) or bin(1) ); -- gt9

    bcdout_temp(3) <=  not bcdout_temp(4) and bin(3);   --  zero if gt9 

    bcdout_temp(2) <=  (    bin(3) and bin(2) and bin(1)) or
                       (not bin(3) and bin(2));

    bcdout_temp(1) <= (    bcdout_temp(4) and not bin(1)) or -- gt9 XOR bin(1)
                      (not bcdout_temp(4) and     bin(1));

    bcdout_temp(0) <= bin(0);                           -- doesn't change

REG5:
    process (clk)
    begin
        if clk'event and clk = '1' then
            bcdout <= bcdout_temp;
        end if;
    end process;
end architecture;

library ieee;
use ieee.numeric_bit.all;

entity bin2bcd_tb is
end entity;

architecture foo of bin2bcd_tb is
    signal bin:         bit_vector(3 downto 0);
    signal clk:         bit;
    signal bcdout:      bit_vector(4 downto 0);
begin

DUT:
    entity work. bin2bcd (dataflow)
        port map (
            bin => bin,
            clk => clk,
            bcdout => bcdout
        );

CLOCK:
    process
    begin
        wait for 5 ns;
        clk <= not clk;
        if now > 160 ns then
            wait;
        end if;
    end process;

STIMULI:
    process
    begin
        for i in 0 to 2 ** bin'length - 1 loop
            bin <= bit_vector(to_unsigned(i, bin'length));
            wait for 10 ns;
        end loop;
        wait;
    end process;
end architecture;

并表明它给出了正确的结果:

bin以十进制显示,bcdout以十六进制显示。