VHDL中相似实体的包装和切换

我想描述一个实体,它既可以正常工作,也可以置于测试模式。我的一般设计是一个顶级实体,它包装了“真实”实体和一个测试实体。

考虑一个小的顶级实体(实际上,还有更多的I/O):

entity toplevelobject is
    port (
        in1 : inout std_logic;
        in2 : inout std_logic;
        out1 : out std_logic;
        out2 : out std_logic;
        testline : in std_logic;
        testclk : in std_logic;
    );

end toplevelobject;

clk 作为输出,甚至 in_* .

architecture test_passthrough of toplevelobject is
    -- This is the actual module
    component real_module
    port (
        in1 : in std_logic;
        in2 : in std_logic;
        out1 : out std_logic;
        out2 : out std_logic;
        clk : in std_logic;
        -- Note absence of "testline"
    );
    end component;

    -- This is the test module, which will just put the clk
    -- signal out on all pins, or play a tune, or something
    component test_module
    port (
        in1 : out std_logic;
        in2 : out std_logic;
        out1 : out std_logic;
        out2 : out std_logic;
        testclk : in std_logic;
        -- Note absence of "testline"
    );
    end component;

    signal real_in1, real_in2 : std_logic;
    signal real_out1, real_out2 : std_logic;

    signal test_in1, test_in2 : std_logic;
    signal test_out1, test_out2 : std_logic;

begin

    real_0 : real_module port map (
        in1 => real_in1,
        in2 => real_in2,
        out1 => real_out1,
        out2 => real_out2,
        clk => clk,
    );

    test_0 : test_module port map (
        in1 => test_in1,
        in2 => test_in2,
        out1 => test_out1,
        out2 => test_out2,
        testclk => clk,
    );

    -- Ports that are outputs on both don't need
    -- much special attention

    out1 <= real_out1 when testline = '0' else test_out1;
    out2 <= real_out2 when testline = '0' else test_out2;

end test_passthrough;

• 对于 inout ports,我应该有一个大的进程吗 case ... when 打开的语句 testline ? 或者每个I/O的进程 if

  passthrough_in1 : process(testline, in1, test_in1) is
  begin
      if testline = '0' then
          real_in1 <= in1;
      else
          in1 <= test_in1;
      end if;
  end process passthrough_in1;
  

…对。。。

    passthrough_all : process(in1, test_in1, in2, test_in2, testline) is

        case testline is
            when '0' =>
                real_in1 <= in1;
                real_in2 <= in2;
            when '1' =>
                in1 <= test_in1;
                in2 <= test_in2;
        end case;

    end process passthrough_all;

• 我不知道我需要什么 passthrough_in1 (甚至 passthrough_all 测试线 ?
• real_in1 / test_in1 在两个包装实体之间进行选择?或者有没有另外一种说法“如果 测试线 高,连接 test_module 输出 in_1 到 toplevelobject 输入/输出 ?